Technical Field
This invention relates generally to the field of semiconductors, and more particularly, to a hardmask used during a halo/extension implant of a SRAM layout for a semiconductor device.
Related Art
A typical integrated circuit (IC) chip includes a stack of several levels or sequentially formed layers of shapes. Each layer is stacked or overlaid on a prior layer and patterned to form the shapes that define devices (e.g., field effect transistors (FETs)) and connect the devices into circuits. In a typical state of the art complementary insulated gate FET process, such as what is normally referred to as CMOS, layers are formed on a wafer to form the devices on a surface of the wafer. Further, the surface may be the surface of a silicon layer on a silicon on insulator (SOI) wafer. A simple FET is formed by the intersection of two shapes, a gate layer rectangle on a silicon island formed from the silicon surface layer. Each of these layers of shapes, also known as mask levels or layers, may be created or printed optically through well known photolithographic masking, developing and level definition, e.g., etching, implanting, deposition, etc.
The FinFET is a transistor design that attempts to overcome the issues of short-channel effect encountered by deep submicron transistors, such as drain-induced barrier lowering (DIBL). Such effects make it harder for the voltage on a gate electrode to deplete the channel underneath and stop the flow of carriers through the channel—in other words, to turn the transistor off. By raising the channel above the surface of the wafer instead of creating the channel just below the surface, it is possible to wrap the gate around all but one of its sides, providing much greater electrostatic control over the carriers within it.
In FinFET technology, device width is defined by fin height and fin number. A 1-1-1 fin type static random access memory (SRAM) cell layout design (i.e., one fin for each pull-down (PD) transistor, pass-gate (PG) transistor, and pull-up (PU) transistor) is desired to achieve a high SRAM cell density. This intrinsically provides a beta ratio (i.e., current (I) ratio of PD/PG) of 1 for FinFET technology based SRAM designs. In standard SRAM designs, a beta ratio >1 is desirable for cell stability. However, it is difficult to tune fin height or use different fin numbers for PD transistors and PG transistors.
Currently, there are two common methods used in an attempt to achieve this the desired beta ratio in SRAM designs. The first method provides different channel widths for PD transistors and PG transistors, while the second method provides an extra channel implant mask for the PG transistor to generate a different PG transistor threshold voltage (Vt). However, adding an extra mask for PG Vt tuning adds additional processing steps, and will induce a different Vt for the PD transistor and PG transistor due to different channel doping levels.
It is further known that during processing, halo/extension implants need to be implanted into the vertical fins at an angle. However, due to the small distances between N and P-type fins in the SRAM layout, the mask blocking effect makes the angled implant difficult. Current approaches focus mainly on reducing implant tilt angles. However, this approach limits implant dosing and/or the engineering design window. Plasma implantation is another current art approach used, but is also undesirable because it suffers from negative process variations.